Commercial FDSOI Quantum Dots Within Different Device Architectures

CMOS technology is critical in developing scalable quantum computers based on Si spin qubits. The use of well-established semiconductor manufacturing processes has the potential to enable high-quality, high-density qubit chips. Moreover, the error rates and coherence times in Si spin qubits make them promising candidates for fault-tolerant quantum computation. While high-fidelity Si spin qubits have been demonstrated in 300mm foundry-compatible technologies, the current state-of-the-art within commercial platforms is limited to quantum dot (QD) charge properties. Making the leap from this to high-fidelity Si spin qubit arrays demands the fabrication of high-quality, reproducible QDs, which is achievable by the optimization of the fabrication process flow. In this work, we study a range of device architectures and process splits to identify the best candidates for qubit arrays, all of which have been fabricated by CMOS foundries on commercially available platforms. We measure linear (1xN) and bilinear (2xN) arrays of FDSOI (Fully Depleted Silicon-On-Insulator) QDs within the many-electron regime using transport across the Si channel. We also use Single-Electron Transistors (SETs) to detect neighboring QDs in the bilinear array down to the few-electron regime. Our results bring us a step closer to a CMOS-based large scale quantum computer.