Charge and spin control of FDSOI quantum dots in a bilinear array
ORAL
Abstract
Today’s small-scale implementations of QEC clearly show that increasing the number of physical qubits with good coherence times, and high-fidelity operations, can lead to an improvement in the logical error rates [1]. Leveraging on decades of semiconductor research, spin qubits offer significant advantage in this regard compared to other platforms. Here we present our latest results on a chip design based on fully depleted – silicon on insulator (FDSOI) technology, manufactured via an industry-compatible CMOS process [2,3]. These devices feature a bilinear array of quantum dots with shared exchange gates. However, the arrays are separated by a trench cut to allow us to operate quantum dots on one side of the array and use a Single Electron Transistor (SET) charge detector on the other side of the array. We will show that we have charge control of these devices such that we are able to load a controlled number of electrons in the quantum dots and operate them in a regime isolated from the reservoirs. We will further show spin signature and manipulation of the quantum dots.
[1] Google Quantum AI et. al., ‘‘Quantum error correction below the surface code threshold,’’ arXiv: 2408.13687, 2024.
[2] Maurand, R. et. al., ‘‘A CMOS silicon spin qubit,’’ Nat. Comm. 7, 13575, 2016.
[3] Urdampilleta, M. et. al., ‘‘Gate-based high fidelity spin readout in a CMOS device,” Nat. Nano. 14, 737-741, 2019.
[1] Google Quantum AI et. al., ‘‘Quantum error correction below the surface code threshold,’’ arXiv: 2408.13687, 2024.
[2] Maurand, R. et. al., ‘‘A CMOS silicon spin qubit,’’ Nat. Comm. 7, 13575, 2016.
[3] Urdampilleta, M. et. al., ‘‘Gate-based high fidelity spin readout in a CMOS device,” Nat. Nano. 14, 737-741, 2019.
*This research was supported by funding from the European Union under the Horizon Europe program, project MCSquare grant number 101136414.
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Presenters
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Jayshankar Nath
- Quobly