Advancing Superconducting Qubits: CMOS-Compatible Processing and Room Temperature Characterization for Scalable Quantum Computing beyond 2D Architectures

CMOS-compatible industry-style processing on 200 mm wafers is crucial for scaling up QPUs (quantum processing units) based on superconducting qubits, enabling precise fabrication and integration into sophisticated 3D architectures. Here, we report on an industry-grade CMOS-compatible qubit fabrication approach using a CMOS pilot line, enabling a yield exceeding 90%, with a qubit frequency spread evaluated across the full wafer diameter of approx. 5% and relaxation times (T1) approaching 85 µs. Furthermore, we conducted a comprehensive analysis of wafer-scale room temperature characteristics collected from multiple wafers and fabrication runs, focusing on resistance measurements and their correlation to low temperature qubit parameters. From this, we notably show a close correlation between qubit junction resistance and frequency in accordance with the Ambegaokar-Baratoff relation. This overarching relation sets the stage for pre-cooldown qubit evaluation and sorting. In particular, such early-on device characterization and validation are crucial for increasing the fabrication yield and qubit frequency targeting, which currently represent major scaling challenges. Furthermore, it enables the fabrication of large multichip quantum systems in the future. Our findings highlight the great potential of CMOS-compatible industry-style fabrication of superconducting qubits for scalable quantum computing in a foundry pilot line cleanroom.