Understanding Low Structural Relaxation in Phase-Change Chalcogenide Superlattices
ORAL
Abstract
Chalcogenides such as Ge2Sb2Te5 (GST) undergo reversible changes between their low-resistance crystalline phase and high-resistance amorphous phase, induced by Joule heating. However, structural relaxation of their amorphous phase leads to unstable electrical resistance over time, known as resistance drift in phase-change memory (PCM), placing fundamental limits on such data storage [1].
Here, we uncover that resistance drift induced by structural relaxation is strongly suppressed in superlattices of Sb2Te3/GST [2], compared to memory films with only GST. Temperature-dependent electrical measurements of PCM based on such superlattices reveal the conduction activation energy is lowest in superlattices with 2 nm Sb2Te3 and 1.8 nm GST (16 periods), marking low structural relaxation and enabling low resistance drift. However, superlattices with thicker unit layers (e.g. 16 nm Sb2Te3 and 14 nm GST), or with strongly intermixed interfaces, exhibit greater structural relaxation, comparable to bulk GST. This points to the key role of superlattice interfaces in limiting resistance drift, and the fundamental insights obtained here are essential to PCM-based applications [3].
Refs: [1] M. Boniardi et al., Appl. Phys. Lett. (2011). [2] A. I. Khan, E. Pop et al., Nano Letters (2022). [3] A. I. Khan, E. Pop et al., Science (2021).
Here, we uncover that resistance drift induced by structural relaxation is strongly suppressed in superlattices of Sb2Te3/GST [2], compared to memory films with only GST. Temperature-dependent electrical measurements of PCM based on such superlattices reveal the conduction activation energy is lowest in superlattices with 2 nm Sb2Te3 and 1.8 nm GST (16 periods), marking low structural relaxation and enabling low resistance drift. However, superlattices with thicker unit layers (e.g. 16 nm Sb2Te3 and 14 nm GST), or with strongly intermixed interfaces, exhibit greater structural relaxation, comparable to bulk GST. This points to the key role of superlattice interfaces in limiting resistance drift, and the fundamental insights obtained here are essential to PCM-based applications [3].
Refs: [1] M. Boniardi et al., Appl. Phys. Lett. (2011). [2] A. I. Khan, E. Pop et al., Nano Letters (2022). [3] A. I. Khan, E. Pop et al., Science (2021).
*This work was supported in part by the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), in part by the Semiconductor Research Corporation (SRC) and in part by the Institute for Basic Science under Grant IBSR019-D1.
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Presenters
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Xiangjin Wu
- Stanford University
- Stanford University, USA