A 200 mm Wafer Size Superconducting Qubit Foundry at MIT Lincoln Laboratory
ORAL
Abstract
MIT Lincoln Laboratory has worked over the course of more than a decade to establish robust, reliable superconducting qubit fabrication processes. Recently, we have piloted a superconducting foundry model to provide access of its robust, high-yielding process to the US quantum research and development community. Initially established on 50 mm silicon wafers, we have ported our core process to the Laboratory's 90 nm capable, Class-10, 200 mm wafer size Microelectronics Laboratory (ML). This Trusted, ISO9001 facility contains automated cluster tools with improved process resolution and control, automated defect inspection and characterization for improved yield, in-line metrology, and additional real estate to accommodate multiuser runs. We will discuss the development of this 200 mm process, in particular the development of a superconducting air bridge process and of a flip-chip process for 2-D chip stacking.
*This material is based upon work supported by the Department of Defense under Air Force Contract No. FA8702-15-D-0001. Any opinions, findings, conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Department of Defense.
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Presenters
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Jeffrey Knecht
- MIT Lincoln Lab
- MIT Lincoln Laboratory