Error mitigated parity quantum optimization

The LHZ/parity architecture can encode industrial-relevant optimization problems on near-term quantum devices with fully programmable planar chips. However, running quantum optimization algorithms on the LHZ/parity architecture still requires developing error mitigation techniques to cope with hardware decoherence and dephasing processes. We propose a novel approach that exploits the architecture's intrinsic structure to mitigate bit-flip errors. We present numerical simulations of the quantum approximate optimization algorithm (QAOA), suggesting that our error mitigation scheme will significantly enhance the algorithm's performance on noisy quantum hardware.