Stochastic logic in thermodynamically consistent circuit models

In this talk I will describe some of our recent efforts to apply a burgeoning understanding of fluctuations in the transport of nanoscale devices to the design of noisy logical gates. Specifically, I will employ recent developments from stochastic thermodynamics, including speed limits and generalized fluctuation-dissipation relations, to elucidate the behavior of a thermodynamically consistent model of a logical circuit based on a generalization of a ressonant level model. The relationship between speed, energy consuption and accuracy will be explored in modular gate architectures of simple circuits like the D Flip-flop and parity checking device. Some principles of the design of low dissipation computing will be discussed.