Robust Quantum Circuit Approximation for Resource-Efficient Circuit Synthesis

ORAL

Abstract

We present a procedure to robustly generate approximations for quantum circuits to reduce their CNOT gate count. Our approach employs circuit partitioning for scalability with procedures to 1) reduce circuit length using approximate synthesis, 2) improve fidelity by running circuits that represent key samples in the approximation space, and 3) reason about approximation upper bound. Our evaluation results indicate that our approach of "dissimilar" approximations provides close fidelity to the original circuit. Overall, the results indicate that the procedure can reduce CNOT gate count by 30-80% on ideal systems and decrease the impact of noise on existing and near-future quantum systems.

*This work was supported by the Office of Science, Office of Advanced Scientific Computing Research Accelerated Research for Quantum Computing Program of the U.S. Department of Energy under Contract No. DE-AC02-05CH11231, Northeastern University, NSF Award 1910601, the Massachusetts Green High Performance Computing Center facility, Oak Ridge Leadership Computing Facility, which is a DOE Office of Science User Facility supported under Contract No. DE-AC05-00OR22725, and IBM Q. The views expressed are those of the authors and do not reflect the official policy or position of IBM or the IBM Q team.

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Publication: Patel, Tirthak, Ed Younis, Costin Iancu, Wibe de Jong, and Devesh Tiwari. "Robust and Resource-Efficient Quantum Circuit Approximation." arXiv preprint arXiv:2108.12714 (2021).

Presenters

  • Tirthak Patel

    • Northeastern University

Authors

  • Tirthak Patel

    • Northeastern University

  • Ed Younis

    • University of California, Berkeley

  • Costin C Iancu

    • Lawrence Berkeley National Laboratory

  • Bert A de Jong

    • Lawrence Berkeley National Laboratory
    • LBNL

  • Devesh Tiwari

    • Northeastern University