Hardware-Efficient Quantum Optimization Layered Algorithms and Experiments

Quantum optimization algorithms, such as QAOA, that implement parametrized stochastic optimization solvers attempt to identify low-energy solutions of Ising systems by exploiting available quantum effects in noisy-intermediate scale machines. Engineering a well-performing parametrized quantum optimization circuit is indeed an exercise in balancing the trade-off between expressivity and implementation complexity. We show that, for MaxCut QAOA circuits defined on native hardware topology (Rigetti’s Aspen Quantum Processors), error-mitigation techniques recover simulated features of the noiseless theory. Moreover, we explore a design space for QAOA-like ansatze that perform well in theory as well as in hardware for fully-connected problems [1]. We also discuss how efficient coherence and entanglement detection methods that could be coupled with quantum optimization experiments require only linear overhead in benchmarking time [2].