Analysis and mitigation of interface losses in transmon qubit

Reducing losses in superconducting qubit circuits is critical for enabling the development of large-scale quantum computing architectures.  Qualitative and quantitative models of qubit performance are a powerful tool for understanding and reducing these losses.  To generate such models, we tailor device geometies and circuit parameters to maximize sensitivity to specific loss mechanisms. These tailored devices function as 'test structures' that can be co-fabricated with standard designs to develop accurate qubit loss models.   We present the results of a series of studies that investigate losses in transmon qubits resulting from capacitor and Josephson junction dielectric layers, fabrication residues, microwave packaging, and background quasiparticles.  As part of this approach, we develop the fabrication processes and EM modeling techniques necessary for accurately modeling dielectric losses.  We furthermore apply these results to improve our qubits and demonstrate mean T₁ and T₂ times in excess of 200 microseconds (Q ~ 4.5 million).