High Fidelity Spin Readout in a CMOS Device

Over the last fifty years, the CMOS (Complementary-Metal-Oxide-Semiconductor) electronics industry has been continuously scaling down transistors in size, to increase performance and reduce power consumption. Nowadays, the smallest transistors in industry achieve 5nm features. As a result, those silicon structures tend to exhibit undesirable quantum effects for a classical transistor which appear to be new research opportunities for quantum information processing.
In particular, it is nowadays possible to trap single electron spins in silicon quantum dots and perform high fidelity quantum gates. These demonstrations combined with the intrinsic properties of the silicon lattice (low spin orbit and hyperfine interaction) make CMOS device an excellent candidate for scalable quantum architectures.
In this presentation, we will show how we can detect a single spin in a CMOS device thanks to an original approach which combines gate-based dispersive charge sensing and a latched Pauli spin blockade mechanism. This scalable method allows us to read out a single spin with a fidelity above 98% for 0.5 ms integration time. Moreover, we show that the demonstrated high read-out fidelity is fully preserved up to 0.5 K. Finally, we will show how these results holds particular relevance for the future co-integration of spin qubits and classical control electronics.