3D integration for superconducting qubits

The superconducting qubit platform has advanced over the past twenty years from fundamental exploration to the deployment of many-qubit systems that support complex algorithms. Along the way, 3D integration has emerged as a critical enabling technology for control and measurement of qubits in an extended array. While 3D integration has long been used in classical computing hardware, the normal metals and lossy dielectrics in these systems are incompatible with high-coherence quantum circuits. 3D integration techniques must therefore be developed and vetted specifically in the context of coherent quantum devices.

Here, we describe a three-tier approach to 3D integration for superconducting qubits, comprising: a planarized, superconducting multilayer metallization chip; an interposer featuring compact, high-aspect ratio, superconducting thru-silicon vias (TSVs); and a qubit chip. These chips are connected to each other via low-loss indium bump bonds. Together, they form a “three-stack” that merges the routing capabilities of the multilayer chip with high-coherence qubits; the interposer provides signal transfer while isolating qubits from lossy dielectrics on the routing chip, and enables new, compact, TSV-integrated circuit element design. I will review the three-stack and its uses, describe experiments that validate the three-stack architecture, and introduce novel circuits and designs that leverage the unique capabilities of the three-stack.