Scalable architecture for next generation superconducting quantum processors

ORAL

Abstract

We discuss a new architecture for superconducting qubits which uses multilevel wiring built off of advanced packaging techniques such as indium bump bonds and through-silicon vias. This architecture improves the scalability of quantum processor design by simplifying I/O routing and reducing crosstalk without sacrificing qubit coherence. Measurement results of a 6-qubit demonstrator chip will be reported, including qubit coherence, pair-wise qubit gate performance and characterization of the individual packaging elements used in the structure.

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Presenters

  • Joseph Suttle

    • IBM TJ Watson Research Center

Authors

  • Joseph Suttle

    • IBM TJ Watson Research Center

  • Neereja Sundaresan

    • IBM TJ Watson Research Center

  • Srikanth Srinivasan

    • IBM Quantum
    • IBM TJ Watson Research Center

  • Joseph Sirianni

    • IBM TJ Watson Research Center

  • Gloria Fraczak

    • IBM TJ Watson Research Center

  • April Carniol

    • IBM TJ Watson Research Center
    • IBM Quantum, Yorktown Heights NY 10598

  • Will Shanks

    • IBM TJ Watson Research Center

  • Eric Lewandowski

    • IBM TJ Watson Research Center

  • John Cotte

    • IBM TJ Watson Research Center

  • Jae-woong Nah

    • IBM TJ Watson Research Center

  • Muir Kumph

    • IBM TJ Watson Research Center
    • IBM Quantum

  • Ricardo Donaton

    • IBM TJ Watson Research Center

  • David W Abraham

    • IBM TJ Watson Research Center