Employing CMOS technology on silicon for a scalable electron-spin qubit architecture

Electrostatically-defined quantum dots (QDs) in silicon are an attractive platform for quantum computation. We propose a scalable qubit device fabricated by industry-compatible processes. The device consists of two dense parallel arrays of QDs localized along a silicon nano-ridge. We implement side-gates and a global back-gate for confinement and a dense metallic top-gate structure for individual control. To minimize potential fluctuations caused by interface roughness and charged defects, the nano-ridge is bounded by atomically-flat {111} facets. According to electrostatic simulations, all QDs can be tuned individually including inter- and intra-array tunnel couplings ranging over multiple orders of magnitude. The most relevant process modules are demonstrated experimentally including anisotropic wet-etching, local oxidation and side-gate formation of the silicon nano-ridge and top-gate fabrication employing the self-aligned spacer process. SiO₂ spacers of 10 nm width on a 50 nm pitch have been achieved. We characterized the atomic flatness of the etched {111} facets and the defect density exhibiting a low Si/SiO₂ interface defect density of ~10¹⁰ V⁻¹cm⁻².
Appl. Sci. 2019, 9(18), 3823