Electrical Characterization of Semiconductor Nanostructure Based Capacitors
POSTER
Abstract
Semiconductor nanostructures are employed as dielectric materials to investigate the performance of a capacitor. We study the effect of geometry and the type and thickness of semiconductors on the total capacitance using electrical measurements. SrTiO3 nano-powder and GaAs and Si nanowires (NW) are chosen for their relatively high dielectric constant. For capacitor plates we deposit ~30 nm Au on both solid glass and flexible PMMA substrate using an electron beam deposition system. The vertically aligned 50 nm diameter GaAs NWs were grown using the Au catalyzed vapor-liquid-solid method. The Si NWs are randomly oriented with an average diameter of 70 nm. The SrTiO3 nano-particles are cubical with a width of around 30 nm. Parallel arrays of GaAs NWs, as well as a random distribution of Si NWs or SrTiO3 nano-powder, lying between two Au coated substrate is composing the capacitors. Capacitance measurements on the reference sample, Au plates with air dielectric spacer, reveal capacitance in the pico-Farad order at room temperature. Capacitor structures with semiconductor dielectrics however show an enhancement of the total capacitance, mainly explained by the semiconductor spacer weakening the effective internal electric.
*The support of the 4VA at JMU is kindly acknowledged.
Presenters
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Masoud Kaveh-Baghbadorani
- Department of Physics and Astronomy, James Madison University, Harrisonburg, Virginia 22807, U.S.A.
- Department of Physics and Astronomy, James Madison University