An extensible circuit QED architecture for quantum computation

COFFEE_KLATCH  · Invited

Abstract

Realizing a logical qubit robust to single errors in its constituent physical elements is an immediate challenge for quantum information processing platforms. A longer-term challenge will be achieving quantum fault tolerance, i.e., improving logical qubit resilience by increasing redundancy in the underlying quantum error correction code (QEC). In QuTech, we target these challenges in collaboration with industrial and academic partners. I will present the circuit QED quantum hardware, room-temperature control electronics, and software components of the complete architecture. I will show the extensibility of each component to the Surface-17 and -49 circuits needed to reach the objectives with surface-code QEC, and provide an overview of latest developments.

*Research funded by IARPA and Intel Corporation.

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Authors

  • Leonardo DiCarlo

    • QuTech and Kavli Institute of Nanoscience, TU Delft, The Netherlands
    • QuTech and Kavli Institute of Nanoscience, Delft University of Technology, The Netherlands
    • QuTech and the Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands
    • QuTech and Kavli Institute of Nanoscience, Delft University of Technology and Intel Corporation
    • QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands
    • QuTech and Kavli Institute of Nanoscience, Delft University of Technology