Extensible circuit QED processor architecture with vertical I/O

ORAL

Abstract

Achieving quantum fault tolerance in an extensible architecture is an outstanding challenge across experimental quantum computing platforms today. Traditionally, circuit QED processors have millimeter dimensions and lateral coupling for all input/output (I/O) signals, precluding the increase in qubit numbers beyond \textasciitilde 10. We present a scalable footprint for circuit QED processors with vertically coupled I/O. Our demonstration using centimeter scale chips can accommodate the \textasciitilde 50 qubits needed in next-generation processors targeting the experimental demonstration of quantum fault tolerance.

*We acknowledge funding from FOM, NWO and the EU FP7 Project SCALEQIT

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Authors

  • Alessandro Bruno

    • QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands

  • Stefano Poletto

    • QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands

  • Nadia Haider

    • QuTech, Delft University of Technology, and Netherlands Organisation for Applied Scientific Research (TNO), Delft, The Netherlands

  • Leo DiCarlo

    • QuTech and Kavli Institute of Nanoscience, Delft University of Technology, Delft, The Netherlands