Vertical gating of sketched nanodevices

Conductive-atomic force microscope (c-AFM) lithography at the LaAlO$_3$/SrTiO$_3$ interface has enabled the creation of various classes of nanostructures, such as nanoscale transistors\footnote{C. Cen, \textit{et al.}, Science \textbf{323}, 1026 (2009).}, single-electron transistors\footnote{G. L. Cheng, \textit{et al.}, Nature Nanotechnology \textbf{6}, 343 (2011).} and has proven to be a promising testbed for mesoscopic physics\footnote{G. L. Cheng, \textit{et al.}, Nature \textbf{521}, 196 (2015).}. To date, these devices have used lithographically-defined side gates, which are limited by leakage currents. To reduce leakage and improve the electric field effect, we have investigated nanostructures with in-situ grown gold top gate. We will discuss designs of logic devices such as inverters, NAND, and NOR gates. In the quantum regime, we compare the performance of in-situ vertical top gates and that of written coplanar side gates with Quantum Dot devices.