Combination of conductance oscillation in the quantum Hall regime and charge trap flash memory phenomena in graphene field effect transistor

We present the feature of conductance oscillation in the quantum Hall regime graphene FET on top of large gate-voltage hysteresis (up to 100 V). A mono-layer graphene was put on the hBN flake on the wet silicon oxide/silicon substrate. At 300 K, the normal conductance versus gate-voltage curve was observed showing the charge neutrality point without hysteresis. At 2 K, however, there was a huge conductance hysteresis during the sweep of gate-voltage, which could be attributed to the characteristics of charge-trap memory behavior because of defects located inside the dielectric playing a role of charge-trap sites. Even though the hysteresis during gate-voltage sweeping was enormous, in our device having hBN for graphene device preventing the deteriorating impacts from the defective SiO$_{\mathrm{2}}$, the conductance oscillation during the gate-voltage sweep was observed from the magnetic field 4 T. In summary, the results proved that the combination of quantum Hall related transport phenomena and the charge-trap memory operation was achieved successfully without affecting each other in our graphene-on-hBN FET device.