Novel Patterning Approaches for Continued Device Scaling

COFFEE_KLATCH  · Invited

Abstract

Top-down patterning techniques based on optical lithography have made semiconductor products ever more powerful, ubiquitous and affordable. This is largely due to the ability of conventional lithographic techniques to transfer trillions of mask features to wafers at defect densities approaching virtually zero in high-volume manufacturing. As features continue to shrink, the ability to print and to correctly place tight-pitch patterns have quickly emerged as two of the greatest challenges to scaling. Given the fundamental physical limitations of conventional optical lithography, complimentary patterning techniques and bottom-up patterning approaches are needed to overcome shortcomings in resolution and pattern placement accuracy. This presentation will focus on the enabling role novel materials can play in achieving both critical dimension scaling and reduced pattern placement errors. The talk will first outline how extreme UV lithography (EUV) and directed self-assembly (DSA) can simplify patterning and improve multilayer pattern placement by reducing the number of masks and associated overlay steps required to achieve the desired resolution. Novel EUV resist materials require amplification mechanisms that overcome acid blur and new strategies to improve shot noise limitations and mechanical stability. For DSA, novel block co-polymers are needed with a higher chi parameter to yield tighter pitch and improved roughness. The second part of the talk will highlight opportunities for self-aligned patterning with a special emphasis on the emerging field of selective deposition. Atomic layer deposition (ALD) is derived from the chemical nature of precursors and co-reactants. The ability of these molecules to recognize chemical functionalities of surfaces, results in the deposition of thin films only where they are desired. Selective deposition is a powerful and so far unexploited patterning tool capable of further reducing or even eliminating pattern placement errors.

Authors

  • Florian Gstrein

    • Intel Corporation