Quantifying Surface Loss Induced by Anti-Vortex Hole Arrays in Planar Superconducting Circuits for Quantum Computation

Two important dissipation sources in superconducting circuits operated at low power are surface loss from two level systems (TLS) and magnetic vortex loss. By patterning the superconducting electrodes with an array of holes, it is possible to reduce or eliminate loss due to magnetic vortices. However, since the highest levels of coherence in planar superconducting circuits have been achieved by improving the electrode-substrate interface, it is natural to expect that adding hole arrays to the electrodes may cause excess surface loss. We present simulations predicting the excess loss magnitude to be $<10\%$ for typical ground plane hole arrays, but for extreme cases of hole size or placement the loss may be much greater. We confirm the simulation result with measurements of high quality factor resonators ($Q_{i}$ $>$ $10^{6}$) with and without the hole patterns.