Towards Multiple-Bit-Per-Cell Operation In a Single Active Layer-Phase Change Memory Cell

High contrast between 0 and 1 logic states in addition to other superior properties of phase change memory (PCM) brought out the possible application of multiple logic levels in a single bit in an effort to boost data storage density. The potential stabilization of resistance levels in between the 0 polycrystalline and 1 amorphous states enables storage of several data in a single device cell (such as 00, 01,10,11 levels). Here we report our investigation of the role of contact geometry and fabrication induced modification of phase change kinetics in stabilizing mixed phase states in an effort to obtain such multiple-bit per cell operation within a single layer PCM material system (Ge$_{\mathrm{2}}$Sb$_{\mathrm{2}}$Te$_{\mathrm{5}})$. The nature of switching dynamics appears highly sensitive to exact programming current distribution and defect density such that a nanoscale square contact with effective current localization at the sharp corners facilitates the formation of stable intermediate phases as compared to a circular one. Resistance maps show that the top contact geometry and engineering of defects can be used as an effective handle to tune the resistance states to optimize memory cells for ultra-high density storage.