Valley Splitting in Electrostatically Confined Structures at the Si/SiO$_2$ Interface

Silicon is a promising material for qubits that use the spin degree of freedom for their encoding because of the anticipated long spin decoherence times. Electrostatic confinement of electrons at a Si(100)/dielectric interface splits the 6 fold conduction band degeneracy. However, 2DEGs are found to have a relatively small valley splitting between the two lowest levels, which is smaller than predicted for ideal interfaces. Small valley splitting is undesirable as it may detrimentally impact the spin decoherence time. Recent theory suggests that interface properties (e.g., miscut and disorder) can significantly change the valley splitting. Large splitting of the valley states has recently been observed in nanostructures formed in Si/SiGe heterostructures for which it is believed the electrons sampled a small number of atomic terraces [1]. In this talk, we will discuss valley splitting at a Si/SiO$_2$ interface in both conventional MOSFETs, MOS- nanostructures and their dependence on effects such as interface roughness, fixed charge, trap density and strain. The valley splitting is characterized via activation energy measurements in the quantum Hall regime. [1] S. Goswami et al., Nature Physics 3, 41 (2007). Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States DOE under contract DE-AC04- 94AL85000.