Vertically coupled Al and Si SETs for characterization of MOS structures at low temperature

Due to impurities and interface states, a silicon metal-oxide-semiconductor field-effect transistor (MOSFET) channel is usually imperfect. A single electron transistor (SET) close to the channel provides a useful probe of these imperfections at low temperatures, the regime where Si devices may be used for quantum information processing. We incorporate an Al-AlO$_{x}$-Al SET as the gate of a narrow MOSFET to induce a self-aligned and vertically coupled Si SET at the Si/SiO$_{2}$ interface [1]. We use this SET sandwich architecture to probe and identify sources of defect charge motion in MOS structures via a cross-correlation measurement between the two SETs. In particular, we will present preliminary data from these devices to study a single charge defect at the Si/SiO$_{2}$ interface. [1] L. Sun, K. R. Brown, and B. E. Kane, Appl. Phys. Lett. \textbf{91}, 142117 (2007).