Characterization of scalable ion traps for quantum computation

We discuss the experimental characterization of several scalable ion trap architectures for quantum information processing. We have developed an apparatus for testing planar ion trap chips \footnote{S. Seidelin \emph{et al.}, Phys. Rev. Lett. \textbf{96}, 253003 (2006).}$^,$\footnote{ J. Kim, \emph{et al.}, Quantum Inf. Comput. \textbf{5}, 515 (2005).}, which features: a standardized chip carrier for ease of interchanging traps, a single-laser Raman cooling scheme, and photo-ionization loading of Mg$^+$ ions. The primary benchmark for a given trap is the heating rate of the ion motional degrees of freedom, which can reduce multi-ion quantum gate fidelities. As the heating rate depends on the ion trap geometry and materials, our testing apparatus allows for efficient iteration and optimization of trap parameters. With the recent ability to fabricate planar traps with sufficiently low heating rates for quantum computation $^2$, we describe current results on the simulation and fabrication of planar traps with multiple intersecting trapping zones for versatile ion choreography.