Si nanowire FET arrays: nano-scale logic and electron transport

In the drive to develop an alternative to conventional CMOS-based computing there are a number of technical and scientific hurdles. Reducing individual device size, while critical, will provide limited gains unless concurrent issues such as device pitch and power dissipation are also addressed. Here, we present an integrated scheme for the fabrication of nano-scale circuits that has the potential to integrate logic, memory, and routing at narrow device pitch within a fault-tolerant architecture. The platform for our approach is based on the SNAP technique, which allows for the fabrication of both metal and semiconducting nanowire arrays at 35 nm pitch, aspect ratios of 10$^{6}$, and wire widths down to 10 nm. Using this process, we are able to fabricate arrays of nano-FETs whose size (100 nm by 10 nm) and spacing (35 nm pitch) allow for dramatically reduced circuit densities (down to $\sim $ 10$^{11}$ elements/cm$^{2})$. We present characterization of these arrays as well as the demonstration of a number of implementations including logic arrays and multiplexing.