Ion Trap in a Semiconductor Chip

Current ion trap research is largely driven by the quest to build a quantum information processor, where quantum bits of information are stored in individual atomic ions and connected through a common interaction with their collective motion$^{1}$. Semiconductor processing techniques, particularly photolithography on integrated structures, allows the fabrication of ion traps which can host large numbers of qubits and shuttle ions between many separated trapping zones$^{2}$. Here we discuss the trapping of a single ion in an rf Paul trap fabricated on a monolithic GaAs heterostructure. Of particular note is that this trap is integrated on a chip and does not require any alignment or manual assembly. In addition to discussing the processing steps and electrical characteristics of the trap, we report measurements of heating of a single ion in the trap$^{3}$. Work supported by the Disruptive Technology Office under Army Research Office contract \newline and the National Science Foundation ITR Program. 1. Cirac, J. I. {\&} Zoller, P. Quantum computations with cold trapped ions. \textit{Phys Rev. Lett.} \textbf{74}, 4091-4094 (1995). 2. Kielpinski, D., Monroe, C., Wineland D. J. Architecture for a large scale ion trap quantum computer. \textit{Nature} \textbf{417}, 709-711 (2002). 3. D. Stick, W. K. Hensinger, S. Olmschenk, M. J. Madsen, K. Schwab, C. Monroe. \textit{Nature Phys.} \textbf{2}, 36-39 (2006).